A Partitioned Translation Lookaside Buffer Approach to Reducing Address Bandwidth
本文档由 enbook 分享于2010-10-09 00:15
This paper presents a simple modication of a computing system s virtual memory hardware that can sharply reduce the number of pins required to transmit address information between a single chip processor and off-chip memory. By partitioning the virtual memory system s translation lookaside buffer (TLB) so that the virtual page numbers are stored in a cache on the processor chi..
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君,已阅读到文档的结尾了呢~~